In RF and microwave applications, due to good linearity, low losses and good integration, SOI process is used to implement switches, power amplifiers, low noise amplifiers, attenuators and phase shifters etc. In these applications, a positive voltage generator (PVG) which voltage is higher than power supply voltage and a negative voltage generator (NVG) which voltage is lower than ground voltage are widely used to increase the dynamic range of the processing power, achieve effective switch under DC bias conditions and lower static current in off state.
The positive voltage generation circuit in existing PVG and the negative voltage generation circuit in existing NVG mainly adopt charge pump circuit to complete voltage boost and generate negative voltage. In basic charge pump circuit, it is necessary to have a plurality of switches to control the directions of charging and discharging of capacitor; at the same time, in order to reduce ripple and switch losses, the size of the transistor switch that controls the charging and discharging of the capacitor must be large enough to reduce on-resistance, therefore, the existing positive/negative voltage generation circuit will take a larger chip area.
FIG. 1 is a schematic view of existing positive voltage generation circuit, as shown in FIG. 1, it comprises four transistor switches M1˜M4, a transfer capacitor C1 and an output capacitor C2. Wherein, the transistor switches M1˜M4 are controlled by control signal S1 and control signal S2 as shown in FIG. 3; wherein, the control signal S1 and the control signal S2 are two-phase non-overlapping clock signals. When the electrical level of control signal S1 is high, transistor switches M1 and M4 are turned on, transistor switches M2 and M3 are turned off. Ignoring transistor switch voltage drop in the on-state, the voltage of transfer capacitor C1 after the charging is finished is equal to the power supply voltage Vdd; when control signal S2 becomes high electrical level, transistor switches M1 and M4 are turned off, transistor switches M2 and M3 are turned on. At this moment, because V2 point is connected to power supply voltage Vdd through transistor switch M3, the charge on transfer capacitor C1 increase the voltage of V1 point to twice that of power supply voltage 2Vdd, and charge output capacitor C2 through transistor switch M2, under the control of control signal S2, the voltage of output capacitor C2 is about twice that of the voltage of the power supply 2Vdd.
FIG. 2 is a schematic view of existing negative voltage generation circuit; similarly, in the negative voltage generation circuit shown in FIG. 2, when control signal S1 is of high electrical level, the transistor switches M1 and M3 are turned on, the voltage of the transfer capacitor C1 is equal to the power supply voltage Vdd; when the control signal S2 is of high electrical level, the transistor switches M2 and M4 are turned on, at this moment, the transistor switch M2 is turned on so that the voltage of V1 point is zero; transfer capacitor C1 pulls the voltage of V2 point to negative power supply voltage −Vdd, at the same time, transistor switch M4 is turned on so that the voltage of VN point which output negative voltage is equal to the voltage of V2 point, that is, equal to the negative power supply voltage −Vdd.
It can be seen from FIGS. 1 and 2, the existing positive voltage generation circuit and negative voltage generation circuit, respectively, needs four larger size transistor switches, a total of eight transistor switches are needed, and the two control signals are two-phase non-overlapping clock signals, the selection of high electrical level or low electrical level for each transistor switch control signals are required to ensure that the gate-source voltage and gate-drain voltage of the transistor switch do not exceed the breakdown voltage of the gate oxide layer, at the same time, additional control signal generation circuit is required to generate the two-phase non-overlapping clock signal as shown in FIG. 3, thus the current positive/negative voltage generation circuit will take a large area on the chip.
In order to prevent overvoltage problem, especially when the switch path is with a DC bias, generally, it requires additional voltage offset circuit to ensure that the positive output voltage is lower than twice of power supply voltage 2Vdd, so that the negative output voltage is higher than the negative power supply voltage−Vdd, thus, will further increase the area of the entire positive and negative voltage generation circuit takes on the chip.